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Espressif Systems /ESP32-P4 /I2C0 /CTR

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Interpret as CTR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SDA_FORCE_OUT)SDA_FORCE_OUT 0 (SCL_FORCE_OUT)SCL_FORCE_OUT 0 (SAMPLE_SCL_LEVEL)SAMPLE_SCL_LEVEL 0 (RX_FULL_ACK_LEVEL)RX_FULL_ACK_LEVEL 0 (MS_MODE)MS_MODE 0 (TRANS_START)TRANS_START 0 (TX_LSB_FIRST)TX_LSB_FIRST 0 (RX_LSB_FIRST)RX_LSB_FIRST 0 (CLK_EN)CLK_EN 0 (ARBITRATION_EN)ARBITRATION_EN 0 (FSM_RST)FSM_RST 0 (CONF_UPGATE)CONF_UPGATE 0 (SLV_TX_AUTO_START_EN)SLV_TX_AUTO_START_EN 0 (ADDR_10BIT_RW_CHECK_EN)ADDR_10BIT_RW_CHECK_EN 0 (ADDR_BROADCASTING_EN)ADDR_BROADCASTING_EN

Description

Transmission setting

Fields

SDA_FORCE_OUT

Configures the SDA output mode 1: Direct output,

0: Open drain output.
SCL_FORCE_OUT

Configures the SCL output mode 1: Direct output,

0: Open drain output.
SAMPLE_SCL_LEVEL

Configures the sample mode for SDA. 1: Sample SDA data on the SCL low level.

0: Sample SDA data on the SCL high level.
RX_FULL_ACK_LEVEL

Configures the ACK value that needs to be sent by master when the rx_fifo_cnt has reached the threshold.
MS_MODE

Configures the module as an I2C Master or Slave. 0: Slave

1: Master
TRANS_START

Configures to start sending the data in txfifo for slave. 0: No effect

1: Start
TX_LSB_FIRST

Configures to control the sending order for data needing to be sent. 1: send data from the least significant bit,

0: send data from the most significant bit.
RX_LSB_FIRST

Configures to control the storage order for received data. 1: receive data from the least significant bit

0: receive data from the most significant bit.
CLK_EN

Configures whether to gate clock signal for registers.

0: Force clock on for registers

1: Support clock only when registers are read or written to by software.
ARBITRATION_EN

Configures to enable I2C bus arbitration detection. 0: No effect

1: Enable
FSM_RST

Configures to reset the SCL_FSM. 0: No effect

1: Reset
CONF_UPGATE

Configures this bit for synchronization 0: No effect

1: Synchronize
SLV_TX_AUTO_START_EN

Configures to enable slave to send data automatically 0: Disable

1: Enable
ADDR_10BIT_RW_CHECK_EN

Configures to check if the r/w bit of 10bit addressing consists with I2C protocol. 0: Not check

1: Check
ADDR_BROADCASTING_EN

Configures to support the 7bit general call function. 0: Not support

1: Support

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data